1:4 Demultiplexer Virtual Laboratory

PrayogSetu — Interactive Digital Electronics Experiment
Digital Electronics
EXPERIMENT MODE:
🎛️ Digital Input Controls (1 Data Input + 2 Select Lines)
📡 Single Data Input (D)
D Data Signal Source
⚙️ Select Lines (S1, S0) — Routing Address
S1 MSB Select Line
S0 LSB Select Line
💡 Output LEDs & Selection Indicator MANUAL MODE
Y0 D · S1̅ · S0̅ 1 (HIGH)
Y1 D · S1̅ · S0 0 (LOW)
Y2 D · S1 · S0̅ 0 (LOW)
Y3 D · S1 · S0 0 (LOW)
⚡ 1:4 Demultiplexer Gate-Level Schematic Diagram Interactive Signal Animation & Data Routing Flow
S1 S1̅ S0 S0̅ D: 1 S1: 0 S0: 0 NOT NOT AND0 AND1 AND2 AND3 Y0: 1 Y1: 0 Y2: 0 Y3: 0
🧮 Live Boolean Output Equations Evaluation Real-Time AND Gate Logic Resolution
Output Y0 (AND0) ACTIVE ROUTE
Y0 = D · S1̅ · S0̅
1 · 1 · 1 = 1
Output Y1 (AND1) INACTIVE
Y1 = D · S1̅ · S0
1 · 1 · 0 = 0
Output Y2 (AND2) INACTIVE
Y2 = D · S1 · S0̅
1 · 0 · 1 = 0
Output Y3 (AND3) INACTIVE
Y3 = D · S1 · S0
1 · 0 · 0 = 0
Current Data Distribution Summary: Data Input D (1) is routed directly to output line Y0 because select lines S1=0 and S0=0. All non-selected outputs (Y1, Y2, Y3) remain at logic 0.
📊 Educational Truth Table — 1:4 Demultiplexer Click any row to load its state into the simulator
INPUTS OUTPUTS SELECTED OUTPUT LINE
Data (D) S1 (MSB) S0 (LSB) Y0 Y1 Y2 Y3
0 0 0 0 0 0 0 Y0 = D (0)
0 0 1 0 0 0 0 Y1 = D (0)
0 1 0 0 0 0 0 Y2 = D (0)
0 1 1 0 0 0 0 Y3 = D (0)
1 0 0 1 0 0 0 Y0 = D (1) ★
1 0 1 0 1 0 0 Y1 = D (1)
1 1 0 0 0 1 0 Y2 = D (1)
1 1 1 0 0 0 1 Y3 = D (1)
📖 Comprehensive Educational Guide & Reference

🔹 What is a Demultiplexer (DEMUX)?

A Demultiplexer (DEMUX) is a combinational logic circuit designed to take a single data input signal and route it to one of multiple output lines based on the binary combination of select (control) lines.

It performs the exact inverse operation of a Multiplexer (MUX). While a MUX acts as a data selector (many inputs to one output), a DEMUX acts as a data distributor (one input to many outputs).

⚙️ Working Principle of 1:4 DEMUX

A 1:4 Demultiplexer has 1 Data Input (D), 2 Select Lines (S1, S0), and 4 Output Lines (Y0, Y1, Y2, Y3).

  • When S1=0, S0=0, input D is routed to output Y0.
  • When S1=0, S0=1, input D is routed to output Y1.
  • When S1=1, S0=0, input D is routed to output Y2.
  • When S1=1, S0=1, input D is routed to output Y3.

Note: If D = 0, all output lines remain at logic 0 regardless of the select line binary combination.

⚡ Gate-Level Circuit Architecture

The standard 1:4 Demultiplexer circuit is implemented using 2 NOT gates (to invert select lines S1 and S0) and 4 3-input AND gates.

The Boolean expressions for the four outputs are:

Y0 = D · S1 · S0
Y1 = D · S1 · S0
Y2 = D · S1 · S0
Y3 = D · S1 · S0

Notice that no OR gate is required in a 1:4 Demultiplexer because each AND gate directly drives an independent output line.

🔄 Multiplexer vs. Demultiplexer Comparison

MULTIPLEXER (MUX)

Many Inputs → 1 Output

Acts as a Data Selector

Selects 1 from 2n input channels using n select lines.

Requires an OR gate at the output stage.

DEMULTIPLEXER (DEMUX)

1 Input → Many Outputs

Acts as a Data Distributor

Routes 1 data input to 1 of 2n output lines using n select lines.

Direct output per AND gate (No OR gate required).

🚀 Real-World Applications of Demultiplexers

📡

Communication Systems

Used to distribute received serial data streams to multiple parallel destination channels.

🔀

Serial-to-Parallel Converters

Converts incoming single-wire serial transmission back into multi-bit parallel data buses.

🖥️

Digital Switching & Routing

Routes clock or data signals to specific memory banks, peripheral devices, or ALU registers.

💾

Address Decoding

Functions as a decoder to select specific memory IC chip enables or register locations.